source: MarkedWired news
TORONTO, ONTARIO–(Marketwired – Nov. 14, 2016) – EEStor Corporation (TSX VENTURE:ESU) (“EEStor” or the “Company”), today announced the completion of the fourth phase of testing of its composite modified barium titanate (“CMBT”) -based energy storage technology. This current phase of testing supports that the Company continues to make significant improvements to its products over previous phases, as well as demonstrates the unique “stacking effect” of its technology.
The stacking effect enables increased energy storage times which positions the technology to directly compete as a market-leading solution in grid-related storage applications. An in-depth analysis of this stacking effect and related market impact can be found in the Company’s white paper which is available for download at www.eestorcorp.com/stacking and at www.sedar.com.
Significantly, the tesing and associated improvements have been achieved using EEStor’s conventional epoxy host polymer. Development of highly polar host polymer versions, particularly targeted at high energy density applications, are being conducted in parallel, and the Company expects to announce the results of this development in the near future.
To ensure consistent testing protocols, Phase 4 testing was completed by Intertek Group plc, the same independent testing laboratory which conducted the Company’s previous three phases of product tests. For this round of testing, in addition to testing by Intertek, the Company also completed independent testing of the identical components with MRA Laboratories Inc. (“MRA”) to support Intertek’s results and to successfully benchmark the internal testing regime performed daily at the Company. The Intertek, MRA and internal EEStor results for Phase 4 were consistently within 2-3% of one another.
Ian Clifford, Founder and CEO of the Company commented: “We are extremely pleased with the results and advancements of the technology over the past year. By including MRA in this round of testing, we have complete confidence in the test results. This, alongside increased time constants and capacitance, should accelerate our discussions with potential capacitor partners who rely heavily on these leading testing organizations for validation.” Clifford added: “With the Company’s high energy density work underway, the imperative to realize sustainable and scalable solutions in energy storage has never been greater. I am confident that EEStor will become a leader in electrical energy storage as we continue to develop technology that will help replace non-renewable fossil fuels1 and challenging electrolytic energy storage that has significant safety and scalability concerns.”2
(1) http://www.un.org/press/en/2011/sgsm13998.doc.htm
(2) http://news.mit.edu/2016/battery-challenges-cost-and-performance-1102
Comparison of Four Phases of Testing
When comparing successive iterations of the Company’s technology, as documented in Intertek testing Phases 1 through 3, it is important to note that there are many variables, including area of the part, voltage under test, thickness and number of layers. The first and most obvious improvement from Phase-to-Phase has been the increase in operating voltage and the dielectric strength of the test materials. In Intertek Phase 1 testing, the Company demonstrated the performance characteristics of twenty 1500-volt single layer samples and one 250-volt stack consisting of 6 combined layers. For Phase 2, test voltages increased to 750 volts in a 6-layer stack, and in Phase 3 a 2000 volt 8-layer stack was tested to 3400 volts.
In Phase 4, EEStor had three separate stacks tested by both Intertek and MRA: a 4-layer, 8-layer and 16-layer stack. It also tested two single layer samples representing individual layers used to create the 4, 8 and 16 layer stacks. All parts tested in Phase 4 are 3000 volt components, and the individual layers have been tested by EEStor to 4500 volts, demonstrating that the Company’s technology is now capable of performing at both increased voltage levels and in larger stack layers, with consistent and predictable results.
For a direct comparison of performance improvements in EEStor’s CMBT-based technology, layer C5-1 (the 1500-volt single layer part tested at the highest voltage [2680 volts] in Phase 1 testing) can be directly compared to the single layer samples tested in Phase 4. The single layers in the current test kit have been successfully tested to 4500 Volts DC without failure, establishing a dielectric strength of over 69 volts per micron. By comparison, a review of Intertek Phase 3 results shows the highest voltage test results observed with the 2000 Volt 8-layer stack (S5), which was tested to 3400 volts, resulted in 47 volts per micron. In Phase 4 testing, EEStor successfully tested stacks with twice as many layers (16) with each layer sustaining more applied voltage. In addition to the increased voltage, the resistance and time constants of the stacked parts increased significantly, and leakage current per volt decreased, demonstrating higher production quality in manufacturing.
In addition to confirming increased performance and durability of the Company’s technology, Phase 4 of testing establishes the unique effects and benefits of EEStor’s patent pending stacking design. As illustrated in the Phase 4 results for the 4, 8 and 16 layer stacks, capacitance increases with the number of layers, as expected, but resistance decreases only moderately. Since time constants are a function of the relationship between capacitance and resistance, the stacking effect demonstrates the unique ability to add capacitance without significantly decreasing resistance, resulting in significantly increased time constants. This breakthrough development opens a number of grid storage related markets previously thought to be outside the immediately addressable markets for the Company. Ferroelectric capacitors, predominantly used in these applications, do not benefit from stacking effects due to currents flowing through the dielectric. In contrast, a unique advantage of EEStor’s paraelectric dielectric technology is that when used in a stacked configuration leakage current can be reduced by the buffer current induced in floating nodes. If this architecture was attempted with ferroelectric capacitors the current through the capacitors would disrupt the buffering field, so the capacitors would not exhibit the stacking effect.
For the full test reports please see:
Intertek: http://www.eestorcorp.com/intertek1116.html
MRA: http://www.eestorcorp.com/mra1116.html
The independent test reports have also been filed and are available for download and viewing at www.sedar.com.
As a result of this patent pending stacking methodology, and the resulting field effect and time constant benefits, the Company believes it can build superior capacitors by continuing to increase the number of layers. Increasing the number of layers is a straight forward process for the Company.
With the improvements above that have been demonstrated in the latest round of testing, the Company plans to accelerate its licensing discussions and evaluation kit distribution with interested parties.
