Murata Boosts Silicon Capacitance Density Beyond 1.3 µF/mm²

Murata has extended its product offering for the mobile and High-Performance Computing (HPC) markets with the availability of its latest silicon process technology to fabricate silicon capacitors with a density of 1.3 µF/mm². 

The extremely low ESL (few pH) and low ESR (few mΩ) of these devices support the highest performances of new Power Distribution Networks (PDN) that require low impedance over a wide frequency bandwidth.

As digital ICs evolve to offer more features at lower voltages, resolving issues like noise and voltage fluctuation is critical.

Its less than 40µm profile enables chip designer engineers to embed the silicon capacitor into the package as close to the active die as possible, minimising the current’s effective path length and, thereby, minimising parasitics.

These multi-terminal devices satisfy the various SoC and microprocessor design requirements for multiple terminal capacitor networks. Replacing conventional monolithic ceramic capacitors with multi-terminal silicon devices reduces the total quantity of capacitors required on the board significantly, which improves the compactness of the end design.

Fewer capacitors also results in total savings in both bill of materials and mounting costs.

Murata 3D silicon manufacturing process is explained in this video:

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