Improving SMPS Performance with Thermal Interface Material

The paper “Improving Switched-Mode Power Supplies Performance with Modified Thermal Interface Material” was presented by Víctor Solera, Department of Electronic Engineering, University of Valencia, Spain at the 5th PCNS Passive Components Networking Symposium 9-12th September 2025, Seville, Spain as paper No. 5.3.

Introduction

Switched-mode power supplies (SMPS) are widely used in modern electronics due to their high energy efficiency and compact size.

As power density increases, effective thermal management becomes essential to maintain component reliability and performance. Heatsinks paired with thermal interface materials (TIMs) are standard solutions for dissipating heat.

However, TIMs introduce a new challenge: they can form parasitic capacitances that generate common-mode (CM) currents, leading to electromagnetic interference (EMI) issues. This article investigates the impact of TIMs on EMI in SMPS and explores a hybrid solution—Shielded Thermal Interface Material (Shielded TIM)—to mitigate CM currents without significantly compromising thermal performance.

Key Points

Extended Summary

The article begins with an overview of the growing adoption of SMPS in compact electronic systems. High switching speeds enable increased power density but generate heat that must be managed effectively. Standard solutions involve mounting mosfets to metal heatsinks, often through TIMs like thermal gap fillers, thermal transfer tapes, graphite sheets, graphite foam gaskets, and thermal conductive insulators. Each TIM type provides thermal conduction, surface compliance, and often electrical isolation.

However, TIMs create an unintended electrical effect: they act as dielectrics between conductive surfaces, forming parasitic parallel plate capacitors. In SMPS, this parasitic capacitance is subjected to high dv/dt switching events, resulting in CM currents that can compromise EMC compliance. The extent of this effect depends on the TIM’s thickness, permittivity, and the area of the mosfet baseplate.

To address this issue, the study introduces a hybrid material called Shielded TIM. It consists of two thermal conductive insulator layers sandwiching a copper foil, which is connected to the mosfet source. This configuration divides the parasitic capacitance into two series segments, effectively reducing the CM current path to ground. The copper shield also redirects high-frequency currents, reducing the EMI impact.

Experimental validation used a 3.3 V to 10 V boost converter operating at 300 kHz. CM emissions were measured with LISNs and a spectrum analyzer for both a standard TIM and the Shielded TIM. Results showed a substantial reduction in CM current peaks, with improvements up to 30 dB at higher harmonics. Thermal performance tests using thermocouples confirmed that the Shielded TIM maintained comparable steady-state temperatures to a single TIM layer, despite the extra layers.

Additionally, the article demonstrates how TIM parasitic effects can be modeled as equivalent capacitors in simulation. The capacitance is calculated using the standard formula C = ε₀ · εᵣ · A⁄d. Comparing simulation and measurement showed good agreement, enabling EMC risk evaluation during the design phase.

Conclusion

TIMs are essential for SMPS thermal management but can significantly increase CM emissions due to parasitic capacitance. The proposed Shielded TIM solution effectively reduces CM currents while preserving thermal and electrical isolation. Experimental results confirm its EMI advantages and acceptable thermal performance. Furthermore, modeling TIM parasitics in simulations allows designers to predict and mitigate EMI issues early in the design process, supporting reliable and high-performance SMPS designs.

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