Empower Semiconductor has introduced a new generation of embedded silicon capacitors (ECAPs) aimed at improving power delivery networks in high‑current AI and high‑performance computing (HPC) processors.
The silicon capacitor devices integrate high capacitance density directly into the processor package to address power integrity limits that are increasingly difficult to solve with conventional board‑level MLCCs and bulk capacitors.
Key features and benefits
The new ECAP portfolio currently consists of three embedded silicon capacitor devices: EC2005P, EC2025P and EC2006P. These components are designed for integration into AI and HPC processor substrates rather than standard PCB mounting, which shifts the decoupling function physically closer to the die and reduces parasitic effects.
Key characteristics highlighted by Empower include:
- Embedded silicon capacitor technology optimized for package‑level integration in AI‑class and HPC processors.
- Capacitance density up to tens of microfarads in a few square millimeters of silicon footprint, supporting aggressive power integrity targets in advanced SoCs.
- Ultralow equivalent series inductance (ESL), which reduces voltage spikes and droop during fast load transients by minimizing parasitic inductance in the power delivery path.
- Ultralow equivalent series resistance (ESR), helping to reduce ripple and losses, and improving stability of the power delivery network (PDN).
- Wide bandwidth, ultralow impedance behavior, enabling effective decoupling over a broad frequency range from VR switching frequencies up into the GHz range relevant for on‑die load steps.
- Package engineering tuned to meet strict dimensional and tolerance requirements for embedded use within processor substrates and advanced packaging flows.
From an engineering standpoint, the main benefit of this ECAP approach is the ability to concentrate a relatively large effective capacitance in very close proximity to the die’s power pins. This shortens current paths, reduces loop inductance, and allows the PDN to meet tighter noise specifications without excessive numbers of board‑level capacitors.
Typical applications
These ECAP devices are clearly targeted at high‑end digital processing where current densities and transient demands exceed what traditional PCB decoupling can practically handle.
Typical application domains include:
- AI accelerators and AI‑class processors used in data‑center inference and training platforms.
- High‑performance computing CPUs, GPUs and custom SoCs where power delivery is a limiting factor for achievable clock speeds and core counts.
- Advanced chiplet‑based systems where multiple dies share a package, making vertical power delivery and embedded decoupling attractive for managing multi‑rail PDNs.
- Network, storage and other infrastructure ASICs that run at high current and need tight voltage regulation at very fast edge rates.
In these systems, the ECAP devices act as the last, high‑bandwidth decoupling stage at the package level, complementing PCB‑mounted bulk capacitors and MLCC arrays. Designers can therefore view them as an additional PDN layer between on‑die capacitance and board‑level components.
Technical highlights
Empower’s initial ECAP lineup offers three capacitance/size combinations intended to give substrate and package designers flexibility in how they distribute embedded capacitance:
- EC2005P: 9.34 µF nominal capacitance in a 2 mm × 2 mm package.
- EC2025P: 18.68 µF nominal capacitance in a 4 mm × 2 mm package.
- EC2006P: 36.8 µF nominal capacitance in a 4 mm × 4 mm form factor.
Compared to prior silicon‑capacitor generations around ~1 µF/mm² and to advanced MLCC solutions, these new embedded ECAP devices move the density into roughly the 2+ µF/mm² range at the package footprint level, roughly doubling Empower’s previously cited E‑CAP density and staying several times higher than typical MLCC implementations used for decoupling.
All three parts are silicon‑based embedded capacitors tailored for integration into processor substrates rather than standard discrete SMD assembly. Exact electrical and mechanical tolerances, voltage ratings and operating temperature ranges should be taken from the manufacturer’s datasheet for each device.
From a PDN design perspective, the combination of relatively high capacitance per device with ultralow ESL and ESR enables designers to push the package‑level decoupling pole to higher frequencies while keeping impedance below the target profile for the processor rail. This can reduce the number of discrete MLCCs, simplify PCB layout and help keep the PDN impedance envelope within budget even as load steps become faster and more severe.
Design‑in notes for engineers
Embedded silicon capacitors such as Empower’s ECAPs change the way decoupling is partitioned between the die, package and PCB. When considering these parts for new designs or platform updates, engineers may want to focus on a few practical aspects:
- PDN stack planning
- Treat ECAP devices as the package‑level high‑bandwidth decoupling layer, sitting between on‑die capacitance and PCB MLCC/bulk stages.
- Start with the processor vendor’s PDN target impedance and allocate how much of that budget is handled by die, package (ECAPs) and board levels.
- Capacitance budgeting and placement
- Use EC2005P, EC2025P and EC2006P as modular building blocks to reach the total embedded capacitance requirement, trading off number of sites versus substrate area.
- Placement within the substrate should minimize loop inductance to the relevant power bumps and maintain symmetry where needed for multi‑rail or multi‑die layouts.
- ESL/ESR interaction with VRM and MLCCs
- Ultralow ESL and ESR help flatten the impedance profile but can also interact with board‑level MLCCs and voltage regulators; transient simulations are recommended to avoid unwanted resonances.
- Include realistic models of the ECAP devices (from Empower’s datasheets or application notes) in PDN simulation tools to verify impedance across frequency and under worst‑case load steps.
- Substrate and assembly considerations
- Because these capacitors are embedded, mechanical and dimensional tolerances of the packages must align with the substrate manufacturing process; layout rules and stack‑up details should be confirmed with the substrate vendor.
- Thermal design should consider any power dissipation in the embedded capacitors, especially in very high‑current rails or when operating at elevated junction temperatures.
- Migration from board‑level decoupling
- For existing platforms, ECAP‑based designs may allow a reduction in high‑count MLCC arrays close to the processor footprint, easing PCB congestion and potentially improving manufacturability.
- For new AI/HPC platforms, early coordination between silicon, package and PDN teams can maximize the benefit of embedded capacitors and reduce redesign risk late in the project.
As AI‑class processors continue to push current density and transient response requirements, package‑integrated decoupling such as Empower’s ECAP family is likely to become an increasingly important part of the PDN toolbox for system architects and power integrity engineers.
Source
This article summarizes and interprets information released by Empower Semiconductor in an official press release announcing its ECAP embedded silicon capacitor portfolio for next‑generation AI and HPC processors.