This article elaborates on design and calculation of Boost DC/DC converters. The post is based on Würth Elektronik‘s “DC/DC Converter Handbook” that can be ordered from WE website here. Published under permission from Würth Elektronik.
Boost Converter Block Diagram and General Thoughts
The boost converter (step-up converter) is used when the output voltage must be higher than the input voltage. As apparent from Figure 1., the inductor is in the input circuit, which means that this topology has no discontinuous input current.
Because the storage inductor integrates the current over time, it has an almost triangular waveform, but this does not mean that the input side of the converter can be ignored in terms of EMC interference. The necessary input filters can therefore often be dimensioned slightly smaller than with the buck converter, for example. On the output side, a discontinuous, trapezoidal current flows in the boost converter.
It is apparent that the output side of the boost converter is more important from an EMC perspective than with the buck converter topology. The diode commutates hard on the output capacitor to which a discontinuous current is therefore superimposed. Depending on the application, the resulting RF
voltage as well as the low-frequency voltage ripple can interfere with the downstream electronics or is radiated as high-frequency interference. This means a downstream output filter may become necessary.
From Figure 1. it is apparent that the boost converter, like the buck converter, has a critical current loop with a high ΔI/Δt. This current loop is a potential source of differential-mode interference. Likewise, the boost converter has a “hot node” with a high ΔV/Δt that is a source of common-mode interference. The layout rules are therefore the same as for the buck converter.
The GND pads of the input capacitor, the output capacitor, as well as the controller IC (with external low side FET, the source connection), must meet at a single point on the board. This keeps the parasitic current loop (H-field loop antenna) as small as possible.
As with the buck topology, the GND of the optional filter capacitor should be slightly further away at the output to have the quietest possible filter GND reference.
To keep undesirable output voltage fluctuations low, the feedback resistor network should also be placed close to the regulator. The possibly very long feedback trace therefore has a low impedance and is less sensitive to interference. The output voltage for regulation should be tapped at a point as close to the output capacitor as possible.
Example Boost Converter Design and Calculation
storage inductor (double) for a sepic converter
Input voltage: Vin = 5 V nominal
Output voltage: Vout = 12 V
Output current: Iout = 0.5 A max.
Switching frequency: fsw = 500 kHz
Max. bandwidth control loop/crossover frequency: fc = 10 kHz
Forward voltage rectifier diode: VD = 0.4 V
Ripple current factor:
Duty cycle D:
Minimum inductance necessary to maintain the ripple current factor:
Considering a standard inductance value of 15 µH, this results in a ripple current of:
Rated Current Ir:
Often it is sufficient to select the rated current based on the average inductor current (output current at the buck converter) with some margin. In fact, the RMS value of the inductor current (average inductor current + AC ripple current) is responsible for the heat generated at the DC resistor (see RMS chapter in Selection of Storage Inductors for DC/DC Converters).
The input current is estimated here using the output power and the diode conduction losses. As this simplification results in additional errors, e.g., the influence of switching losses on the input current is neglected, the rated current margin for the boost converter should be larger than for the buck converter.
A choke with more than 1.24 A rated current (according to data sheet) should be selected.
Saturation Current Isat:
Half the AC ripple current must be added to the average inductor current to determine the maximum peak current. The average inductor current of the boost converter corresponds to the input current.
You can now select a suitable storage choke based on these results. Some safety margin should also be included, as component tolerance, the actual efficiency and ambient temperature have been not considered here. For this example, an experienced designer selects an inductor with at least 15 µH according to the datasheet, as well as 1.5 A rated current and 1.8 A saturation current.
The fastest and easiest way to get there is to use the REDEXPERT inductor simulation tool.
Input Capacitor for a Boost Converter
RMS current (ripple current) through the input capacitor:
With the help of the REDEXPERT tool, a capacitor can now be selected with the lowest possible impedance at the switching frequency of 500 kHz, which at the same time meets the requirements in terms of ripple current as well as voltage.
Output Capacitor for a Boost Converter
The output capacitor is defined based on the maximum permissible voltage ripple and based on the maximum permissible voltage change (Vdroop) resulting from a load step. In our example we want to have a voltage ripple of maximum 1% (120 mV) at an output voltage of 12 V. Furthermore, the voltage change should not exceed 3% (360 mV) for a load step from 0.1 A to 0.5 A (Istep = 0.4 A).
From these assumptions, the minimum necessary capacitance can be calculated, which fulfills both requirements. For the output voltage residual ripple, in addition to the capacitance-dependent part, the influence of the ESR is considered (the ESL is neglected). For simplicity, an even split is assumed for the two components, resulting in 60 mV each for the capacitance and the ESR calculations. With the boost converter, the extent to which this addition actually occurs, depends on the duty cycle and the magnitude of the ripple current.
In addition, it must be checked mathematically whether the AC current through the output capacitor stays below the maximum ripple current according to the datasheet. The following equation describes the relationship between the output capacitance and the ripple voltage for a boost converter topology (assumption: ideal capacitor):
The next equation is used to calculate the minimum capacitance required for the given capacitance dependent ripple:
For the boost converter topology, the additional calculation is needed to calculate the average current amplitude of the output capacitor current:
The next equation describes the relationship between the ESR of the output capacitor and the ripple voltage for a boost converter topology (assumption: ESL is neglected):
This
This equation is used to calculate the maximum allowable ESR of the output capacitor based on the given ESR-dependent ripple voltage:
This equation is used to calculate the minimum output capacitance to maintain a given voltage droop during a load step:
The next equation is used to determine the RMS current that flows through the output capacitor of the boost converter:
The capacitance of 16.7 µF for the maximum defined voltage ripple is not relevant in this case, as the minimum necessary capacitance of 17.7 µF results from the maximum allowed voltage change during load transients.
Based on the results, we therefore need a capacitor with at least 22 µF (default value) and an ESR lower than 41.7 mΩ at 500 kHz.
A V-chip aluminum polymer SMT capacitor, such as the WCAP-PSLP (875105359003), would be a suitable choice for this purpose. This offers a stable capacitance of 22 µF in a very small package (5.3 · 5.3 · 5.8 mm³), a 16.3 mΩ ESR at 500 kHz and is specified for a ripple current of up to 2.2 A.
Design of the input and output filters for a boost converter
Design is carried out according to the same principle as explained above in the Example Buck Converter Design and Calculation.
Read also the related articles:
- Selection of Capacitors for DC/DC Converters
- Selection of Storage Inductors for DC/DC Converters
- Input filters for DC/DC converters
Buck and Boost Converter Basic Formulas
The following table 1. provides basic formulas of the buck and boost converter topologies.
1) These assumptions apply to the ideal switching regulator in continuous conduction mode
(CCM), i.e., the efficiency of the converter is assumed to be 100% (η = 1).
2) The current curve from this equation is approximately rectangular (ΔI neglected). Exactly:
3) The equations defined for ΔVC,out apply to the ideal capacitor. Cout therefore defines the minimum capacitance to meet the ripple voltage requirement. The actual voltage ripple will be higher due to the parasitic inductance ESL (equivalent series inductance) and ESR (equivalent series resistance) of the capacitor