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Tuesday, February 27, 2024 Duration: 1 hour 2:00PM CET
This webinar is intended for engineers who work on high-speed digital design and test. In particular, we will be discussing PCIe 5.0 / 6.0 and IEEE802.3ck cable test and focussing on signal integrity, performance parameters and automation. Especially PAM4 modulation is very sensitive to noise, crosstalk, and futher disturbances.
You will be learning factors of influence on signal integrity such as insertion and return loss, near end crosstalk (NEXT), far end crosstalk (FEXT), multi-agressors, and more. We will be explaining when you need to characterize and deembed the test fixture and how you can do it effectively. You will learn cable requirements and implementations.
Finally we will be presenting and demonstrating test automation with a complete solution from R&S incl. vector network analyzer, multiport switch matrix, and application software. Practical examples and demonstrations illustrate PCIe 5.0 / 6.0 and IEEE802.3ck cable test made easy, fast, and reliable.
