This paper elaborates on problematic of ceramic capacitors MLCC capacitors cracks – literature survey and practical experiments to develop methodology to induce electrode-to-electrode cracks without deterioration of the capacitor’s immediate electrical parameters. In the next step these capacitors are subjected to thermal vacuum and high temperature life test to evaluate its impact to space flight operating conditions.
The paper was presented by Tomas Zednicek, EPCI European Passive Components Institute, Lanskroun, Czech Republic at the 3rd PCNS 7-10th September 2021, Milano, Italy as paper No.2.2.
SUMMARY AND DISCUSSION
MLCC test capacitors 1812 X7R 22uF 25V were subjected to two type of stress to induce cracks:
1. Thermo-mechanical stress to simulate extreme CTE mismatch load. The load was applied by three cycles of dips into hot solder and liquid nitrogen (dt 440C !).
Results: no microcracks were observed on MLCC body surface, all tested parts electrically passed its specification limits.Cross sectioning of the parts did not find any delamination or cracks inside of the MLCC capacitors inner layers. MLCC capacitors showed high robustness to shock temperature stress. This method may not be suitable to generate cracks inside of the capacitors body.
2. Mechanical stress by sharp pin exposure with defined force to MLCC body surface center to stimulate extreme flex stress.
Results: the mechanical pin causes a local damage to MLCC surface depending to the applied force and radius of the pin. Level of electrical damage was monitored continuously during the applied mechanical force by THD analysis. THD was proofed as the most sensitive method to detect electrical behaviour changes.
Changes in electrical parameters were noted only in the case of use of sharp, low radius pins with visible surface layer damage. In case of blunt pin force applied no impact THD was measured, even at very high force 900N. Some MLCC samples were considerably mechanically damaged by sharp pin, nevertheless there is not necessary a direct link between the level of mechanical damage and electrical deterioration / short circuit.
Cross sectioning of the MLCC capacitors after the pin force mechanical stress confirm presence of delamination and cracks inside the capacitor body. Delamination can present in more layers between the electrode and dielectric length from tenth of millimeter-to-millimeter scale. The cracks may present across the whole dielectric thickness bridging opposite electrodes.
The test sequence aim to induce cracks by two different methods – CTE and mechanical overstress – and expose the test parts mounted on a PCB to space dry heat & thermal vacuum life tests.
Test Results
The MLCC 1812 X7R 22uF 25V capacitors with induced cracks / internal damage exhibited quite high range of failures during exposure to accelerated dry heat and thermal vacuum tests.
The dry heat test running at higher temperature 125°C is showing higher degradation rate of the stressed parts vs the thermal vacuum test. This may be driven by higher test temperature suggesting the temperature acceleration may be one of the key parameters initiating failures. The parts without visible damage stressed by extreme CTE load (group 1) and Flex stress by blunt tool (group 4) did not show any deterioration of electrical parameters after board mounting but begin to electrically fail for high DCL and catastrophic short circuit (R<0.1Ohm) even at initial 500hours of exposure to the dry heat load. Control sample without any stress show some 2% failures at 1000hrs and 10% failures at 2000hrs, nevertheless CTE exposed parts had twice higher percentage of failures at this time.
DCL and SC failures were also observed during thermal vacuum test but only in the case of groups 2 and 3 flex stressed parts by sharp pin with significant mechanical surface damage. Parts without visible damage pass the initial test steps and 2000hours without any electrical failures / minor parametric issues.
DCL histogram do not show any continuous DCL degradation during the test, also there are not many fliers from the main distribution. The typical short circuit with low ohmic failure is of sudden degradation nature – no graduate DCL deterioration within 500h steps is noticed. The SC parts fail from the main DCL distribution at previous measurement step. It is thus impossible to identify such failures by statistical dynamic screening etc. at earlier stage.
ACKNOWLEDGEMENT
The work described in this report was supported by ESA under contract No. 4000131515/20/NL/KML/ig “Reliability Assessment of Cracks in Ceramic Capacitor in Space Condition (Life test under Vacuum) – Impact on Standards”.
REFERENCES
- Teverovsky.A.; „Cracking Problems in Low-Voltage Chip Ceramic Capacitors“, NASA NEPP ASRC Federal Space and Defense, 2018. https://nepp.nasa.gov/files/29931/NEPP-BOK-2018-Teverovsky-Paper-NEPPWeb-BOK-Cracking-MLCC-TN65668.pdf
