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Integrated Passive Devices on Glass at ECTC2017

30.6.2017
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Integrated Passive Devices on Glass at ECTC2017
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source: Solid State Technology news

This week, 2017 ECTC is helt in Orlando, USA, IPD on Glass was one of the presented paper’s topic.

As mobile devices become more functional, they are required to accommodate more frequency bands and meet ever smaller form factor requirements. IPD technology (integrated passive devices) offer smaller for factor and higher performance for RF solutions. For filters, high Q inductors are the key. Glass is a good candidate for substrate because of its low dielectric loss, high thermal stability, high resistivity, and adjustable CTE. Glass also provides the advantage for potential cost effective solutions.

ASE Kaohsiung working with Marvell Santa Clara addressed “Glass Based 3D-IPD Integrated RF ASIC in WLP.”

In a glass base 3D-IPD integrated with RF ASIC the glass wafer acts as a bottom wafer, while the ASIC die is flip chip attached to the frontside of the glass wafer. The ASIC wafer comes with the Cu pillar bump.

The process starts with TGV metallization and filling processes, then, carry on the standard wafer level IPD process to complete the frontside structure. The frontside structure consists of capacitor, re-distribution layer (RDL), and under bump metal (UBM). Then, the wafer is shipped to assembly site for wafer level assembly. Wafer level assembly processes are the chip-to- wafer, for the RF ASIC to attach to bottom glass wafer, and wafer level molding process. After assembly, follows by the backside process to form the 3D inductor and ball pad. Backside process includes glass wafer thinning, and backside RDL and passivation processes. Next step is ball mount and singulation to form the WLCSP. The process flow is shown below:

Marvell 1

Reliability tests confirm that results of SAT and open/short are good, and destructive analysis also show no disconnection issue between TGV and double side metal traces. The high-Q 3D inductor performance was verified through measurement results with two port S-parameter measurement methods with the demonstrated Q factor measured above 60 at 1 GHz for a 3.5nH inductor. 

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