Switched Capacitor Converter Explained

This article provides a switched-capacitor DC-DC converter design guide. Video from prof. Sam Ben-Yaakov explains principle of switched capacitor converter operation and its features.

Introduction

Switched-capacitor (SC) converters translate voltage levels using only switches and capacitors, avoiding magnetic components and enabling compact, integrated, and low-EMI power solutions.

Their operation hinges on periodic charge transfer between capacitors across discrete switching states, yielding discrete conversion ratios, characteristic output resistance, and regime-dependent behavior (slow vs fast switching).

These qualities make SC converters attractive for on-chip regulation, point-of-load conversion, LED drivers, and applications where size, reliability, and low ripple are paramount.

Foundations of Switched-Capacitor Conversion

Charge transfer and conversion ratios

An ideal SC converter achieves fixed conversion ratios determined by its topology (e.g., 2:1 step-down, doubler, inverter). In a classic 2:1 step-down, complementary switch phases alternately charge and then redistribute charge so that the output settles near half of the input under light load; under load, deviation is governed by the converter’s effective output resistance and the load current.

Slow switching limit and fast switching limit

SC behavior is often described in two regimes. In the slow switching limit (SSL), the flying capacitors nearly fully charge/discharge each cycle; output resistance scales inversely with switching frequency and flying capacitance. In the fast switching limit (FSL), capacitors move only small charge per cycle, and losses are dominated by switch resistances and non-idealities. Practical designs operate between these limits, balancing frequency, capacitance, and switch sizing.

Canonical topologies

Core SC topologies include the inverter (producing a negative output), doubler (2×), half (1/2×), and ladder/multi-ratio structures combining stages to realize more granular ratios. Hybrid SC approaches graft small inductors or regulation loops onto SC networks to extend efficiency and load range while preserving compactness.

Topology	Ideal ratio	Polarity	Key traits
2:1 step-down	Vout ≈ Vin/2	Positive	Simple, widely used, good for on-chip regulation
Voltage doubler	Vout ≈ 2·Vin	Positive	Boost without inductors, higher ripple if lightly filtered
Inverter	Vout ≈ −Vin	Negative	Generates bias rails, compact bipolar supplies
Ladder (multi-stage)	Multiple discrete ratios	Positive/Negative	Scalable, finer ratios, higher component count
Hybrid SC	Programmable ratios	Positive	Improved efficiency/load range via auxiliary magnetics or control

Modeling and Performance Metrics

Equivalent output resistance

Effective output resistance, often denoted R_out,eq, captures how the output voltage sags with load current due to finite capacitance and resistive losses. In SSL, R_out,eq is primarily set by flying capacitance and switching frequency; in FSL it is set by the conduction path resistances (switch on-resistance, interconnect, ESR). Designers fit R_out,eq with regime-specific models to predict load regulation and efficiency.

Ripple and transient response

Output ripple is influenced by the flying-capacitor charge packets, output capacitance, and the timing of phases. Larger output capacitance and optimized phase interleaving reduce ripple; transient response depends on how quickly the SC network can deliver incremental charge and how the control loop adjusts phases or ratio selection.

Efficiency limits

Efficiency is bounded by conduction losses in switches, capacitor ESR, control overhead, and the mismatch between the ideal ratio and the required output voltage at a given load (ratio “misalignment”). Hybrid SC designs alleviate misalignment by modulating effective ratio or blending with inductive energy transfer to maintain high efficiency across wider operating ranges.

Metric	SSL dependence	FSL dependence	Design lever
Rout,eq	∝ 1/(Cfly · fSW)	∝ Σ Ron + paths ESR	Increase Cfly or fSW; reduce Ron/ESR
Ripple	Charge packet size and Co	Switch timing skew and ESR	Interleave phases; add Co; improve layout
Efficiency	Capacitor charging losses	Conduction and control losses	Optimize ratio, gate drive, and control

Ideal conversion ratios

Below are MathML expressions for representative ideal ratios used in SC converters (neglecting non-idealities). These serve as targets around which practical designs regulate via control or ratio selection. Vout2:1 = Vin 2 Voutdoubler = 2 ⁢ Vin Voutinv = − Vin

Load regulation via equivalent resistance

A useful first-order relation for load regulation expresses output droop as the product of equivalent resistance and load current. In SSL, the dominant dependence is on flying capacitance and frequency; in FSL, on conduction path resistances. Voutload = M⁢Vin − Routeq ⁢ Ioutdc Routeq,SSL ∝ 1 Cfly ⁢ fSW Routeq,FSL ∝ ∑ Ronpath

Power and efficiency

Output power and efficiency definitions apply as usual, with attention to conduction and capacitive losses. Efficiency is treated against ratio alignment and regime-dependent losses. Pout = Vout ⁢ Iout ,   η = Pout Pin

Design practices and trade-offs

Capacitor selection

Flying capacitors should combine low ESR/ESL, stable capacitance across bias/temperature, and suitable voltage ratings. MLCCs offer density but exhibit DC-bias and temperature dependence; film or specialized integrated capacitors may serve when stability outweighs size. Output capacitors prioritize ripple suppression and transient performance; placement close to the load loop is critical.

Switch network and gate drive

Low on-resistance, minimal charge injection, and synchronized, non-overlapping gate timing limit conduction and switching losses. Interleaving multiple phases reduces ripple and spreads heat, while adaptive dead-time control minimizes cross-conduction without increasing charge errors.

Control, regulation, and ratio selection

SC converters typically regulate by duty/phase modulation, frequency scaling, or discrete ratio selection (e.g., toggling between 2:1 and 3:2). Hybrid SC architectures integrate inductive elements or linear assist to maintain tight regulation when the desired Vout deviates from the ideal ratio, thereby improving efficiency over varying loads and inputs.

Layout and EMI

Short, symmetric loops for the flying-capacitor paths, tight placement of switches and capacitors, and solid return planes reduce parasitics and radiated EMI. Differential routing for complementary paths and careful ground partitioning mitigate common-mode noise. Avoid long traces between flying capacitors and switches to preserve FSL performance.

Design lever	Primary benefit	Main caveat
Increase Cfly	Lower Rout,eq in SSL	Area, cost, potential DC-bias derating
Raise fSW	Lower ripple and Rout,eq (SSL)	Higher switching losses, control overhead
Reduce Ron	Improves FSL efficiency	Gate drive complexity, silicon area
Interleave phases	Ripple reduction, thermal spreading	Control complexity, timing skew sensitivity
Hybridize topology	Wide-load efficiency, fine regulation	Added components, design complexity

Applications and Selection Guidance

Integrated regulation and point-of-load

On-die or in-package SC regulators deliver high current density with low profile and minimal EMI, ideal for CPUs, ASICs, and RF SoCs. Ratios near the target Vout maximize efficiency; multi-ratio or hybrid SC accommodates dynamic voltage scaling and load transients.

Bias rails and LED drivers

Inverters and doublers generate compact auxiliary rails (e.g., ± rails for analog biasing) and can efficiently drive LEDs when paired with current regulation. Their magnetic-free design reduces weight and increases reliability in space-constrained systems.

Selection checklist

• Ratio alignment: Choose topology whose ideal ratio bounds the required Vout across Vin and load.
• Load range: Size Cfly and switches for the dominant SSL/FSL regime expected in operation.
• Ripple budget: Determine acceptable ripple; interleave phases and right-size Co accordingly.
• Efficiency target: Quantify conduction vs capacitive losses; consider hybridization if needed.
• Physical constraints: Confirm capacitor volume, derating, and thermal density fit the platform.

These practical selection steps tie the underlying SC theory to real-world constraints, ensuring the chosen topology and sizing meet regulation, efficiency, and compliance goals.

Conclusion

Switched-capacitor converters compress power conversion into charge choreography: discrete ratios, regime-aware models, and careful component/control choices deliver compact, low-EMI solutions. Mastery of SSL/FSL behavior, ratio alignment, and hybrid augmentation enables high efficiency over dynamic operating ranges. With disciplined capacitor and switch selection, clean layout, and adaptive control, SC converters serve as a powerful alternative to magnetics for modern integrated and space-constrained systems.

FAQ: Switched Capacitor Converter