Source: ECN article
06/02/2017 by Paul Pickering, Technical Contributor
Paying close attention to PCB layout can go a long way in reducing parasitics. Manufacturers of high-speed analog and digital circuits offer numerous application notes, tutorials, and seminar material on PCB layout best practices: the information from Texas Instruments and Analog Devices is particularly instructive. For digital circuitry, Howard Johnson and Martin Graham have written a well-regarded book on high-speed digital design, appropriately subtitled A Handbook of Black Magic that covers many of these topics.
IC suppliers can help reduce the effects of PCB parasitics, too.
In the digital arena, devices placed in the high-speed data path often employ “flow-through” packaging that helps keep the trace lengths equal between the positive and negative lines of the differential data lanes to avoid impedance mismatch.
In power ICs, manufacturers are working to reduce the effects of internal parasitics from such items as bond wires and pins. Texas Instruments, for example, offers its PowerStack technology that places two NexFET power transistors directly on top of each other in a three-dimensional package; this arrangement virtually eliminates resistance and parasitic inductance between the FETs. In a synchronous buck converter, that translates to lower common source inductance, resulting in lower switching losses and higher efficiency.
There’s a popular quote, usually (though erroneously) attributed to Mark Twain: “It ain’t what you don’t know that gets you into trouble. It’s what you know for sure that just ain’t so.”
Paying attention to the effects of the PCB on your high-speed design will not only keep you out of the second category, it might also avoid a plague. In this case, of late nights, lost weekends, and angry bosses.
Best of luck with the frogs and the rest. Although I do like a plate of cuisses de grenouille now and then. Locusts, not so much.