Time-dependent capacitance drift of X7R MLCCs under exposure to a constant DC Bias Voltage is one of electronic hardware designers concerns. Vishay publishes its comparative white paper study on this subject.
Vishay White Paper written by Paul Coppens, Eli Bershadsky, John Rogers, and Brian Ward
Until recently, it was assumed that multilayer ceramic capacitor (MLCC) manufacturers’ data stating the typical voltage coefficient of capacitance (VCC) and capacitance loss due to aging (no bias) could be additive, and that further capacitance drift over time will not be significant. However, recent research of the time-dependent capacitance drift of X7R MLCCs under exposure to a constant DC bias voltage – referred to as DC bias aging – has shown there is a time-related capacitance drift that can be much larger than the typical VCC and normal aging effect combined. Further, during PCNS conference an automotive manufacturer reported an issue in critical systems that was related to capacitance loss and DC/AC bias aging .
This issue prompted Vishay to conduct a comparative study of DC bias aging on four manufacturers’ 0603 X7R 100 nF, 50 V MLCCs. Vishay and three other manufacturers’ MLCCs were subjected to 40 % and 100 % of their rated voltage for DC bias aging analysis, which spanned over 1000 hours. After periodic intervals of time, the capacitance was measured on all samples with the same DC bias voltage level applied. Results confirmed that prolonged exposure of X7R capacitors to a DC bias voltage leads to a capacitance decrease that is much stronger than the natural drift due to aging.
All competitors’ capacitors show a greater rate of capacitance loss over time compared to Vishay capacitors. Beyond 1000 hours, the Vishay capacitors have the highest remaining capacitance. It was also observed that once bias is removed, Vishay’s capacitance recovers much quicker
than competing parts.
For several decades, multilayer ceramic capacitors (MLCC) have been the preferred choice fo r many surface-mount applications because of their high capacitance, low equivalent series resistance, low cost, and insensitivity to high temperature solder assembly. The stability of their electrical characteristics largely depends on the natureof the dielectric material used. The two commonly used types of ceramic dielectrics are class I and class II. Class I – being a very stable, low loss dielectric material based on paraelectric ceramics – allows only a more limited capacitance range because of its relatively low dielectric constant.
Class I capacitors are excluded from this study because of their natural stability with time, temperature, and voltage. Class II has high dielectric constant materials based on ferro-electric ceramic compositions. High capacitance values can be achieved, but at the cost of higher losses and reduced stability of the electrical characteristics. Several factors will affect the stability of the electrical characteristics in class II capacitors. Among these factors, the most well-known are temperature, DC/AC voltage amplitude, frequency, and the aging of capacitance over time.
Although the effects of DC voltage on capacitance and the gradual decrease of capacitance because of unbiased aging are well known in the industry, little to no attention has been paid to the long term effects of applied DC voltage on capacitance over time. Recently this characteristic, termed DC bias aging, received more attention after application problems were encountered. For a better understanding of the mechanisms that lead to DC bias aging, it is helpful to quickly review the specifics of unbiased aging and the VCC effect.
The VCC effect and unbiased aging are specifically related to the ferroelectric nature of class II MLCCs. A characteristic of ferroelectric dielectrics is the appearance of a spontaneous, permanent polarization. As a result of this spontaneous polarization, the dipoles in a ferroelectric crystal tend to line up, giving rise to ferroelectric domains in which all dipoles have the same direction. ,. Since the concentration of domains and dipole alignments directly impact the dielectric constant K, any changes or re-orientation of the domains will influence K, and thus capacitance per the following formula:
C = capacitance
n = number of dielectric layers
A = overlap area of each conductive plate (m2)
εo = dielectric permeability of free space (8.854 x 10-12 F/m)
K = dielectric constant
t = thickness separating each dielectric layer (m