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    Modeling Planar Magnetics Temperature: Practical Guidelines for Power Electronics Engineers

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    Modeling Planar Magnetics Temperature: Practical Guidelines for Power Electronics Engineers

    YAGEO Releases Ferrite Shielded Power Inductors for High‑Density Designs

    Samsung Presents MLCC Selection Guide for Humanoids and Robotic Applications

    AI-Assisted Structural Diagnostics and Physics-Based Reliability Interpretation of Tantalum Capacitor Anodes

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Near Zero Power Temperature Sensing Transistors Enables Next Gen Energy Harvestors with Capacitors

9.10.2017
Reading Time: 2 mins read
A A

source: Machine Design news and Nature.com article

A low-power temperature sensor currently under development at the University of San Diego might lead to sleeker temperature-sensing devices and designs used in wearables, diagnostic sensors for the industrial Internet of Things, and healthcare. The sensors with capacitor based energy accumulation capability would eliminate the need for bulky power supplies, batteries, and last years without having to be recharged.

RelatedPosts

Modeling Planar Magnetics Temperature: Practical Guidelines for Power Electronics Engineers

YAGEO Releases Ferrite Shielded Power Inductors for High‑Density Designs

Samsung Presents MLCC Selection Guide for Humanoids and Robotic Applications

The technology, still in its research phase, takes advantage of a phenomenon called the quantum tunneling effect, which allows very small quantities of electrons to leak through potential barriers in ultra-thin transistors. Though very small, this leakage current is enough to charge two capacitors at reference and temperature-dependent rates, as enabled by the one transistor’s temperature-dependent intrinsic properties. It uses two gate-leakage metal-oxide semiconductor transistors (MOSFETs).

One tradeoff of the low-power design is the relatively low response time of up to 1 temperature reading per second. The team is still developing their technology to address its limitations, but for now, it stands out as pretty impressive. Pictured above, it was integrated onto a very small silicon chip no larger than 0.15 square millimeters.

The sensor described in the work enables transduction and digitization of temperature at 628× lower power than prior-art without a significant reduction in sensing accuracy. By combining the generation of CWT and PTAT voltages via subthreshold-biased 2T circuits with tunneling-current-based CWT resistances to generate CWT and PTAT currents, and using these currents in a feedback circuit that normalizes charging time via a digitally-controlled capacitor bank, temperature was directly digitized at ultra-low-power. With a relaxation oscillator intrinsically built into the proposed architecture, no external references, biases, clocks, or any other components are required for temperature-to-digital transduction. The proposed sensor enables a new class of devices that can monitor their environments with nearly zero power, enabling ultra-long battery life, or energy harvesting from low-power sources towards energy-autonomous operation. While measurements across the four chips presented in this paper gives an idea of the accuracy of the proposed temperature sensor in the presence of process variation, more die-to-die, wafer-to-wafer, and lot-to-lot measurements would be needed in future work to validate accuracy for volume manufacturing.

A further explanation of the research can be read in the paper, “Near-Zero-Power Temperature Sensing via Tunneling Channels Through Complementary Metal-Oxide-Semiconductor Transistors” by Hui Wang and Patrick P. Mercier, published in the journal, Nature.

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