Empower Semiconductor has introduced a new family of embedded silicon capacitors (ECAPs) aimed at solving power integrity challenges directly at the AI and high‑performance computing (HPC) processor package level.
By integrating high‑density capacitance into the processor substrate, these silicon capacitor devices address the limits of traditional board‑level decoupling in systems with extreme current transients and tight voltage margins.
Key features and benefits
The new ECAP portfolio currently includes three embedded silicon capacitors optimized for package‑level integration in AI and HPC SoCs:
- EC2005P: 9.34 µF nominal capacitance in a 2 mm × 2 mm package
- EC2025P: 18.68 µF nominal capacitance in a 4 mm × 2 mm package
- EC2006P: 36.8 µF nominal capacitance in a 4 mm × 4 mm package
From a power integrity perspective, the key characteristics of these ECAP devices are:
- Ultralow equivalent series inductance (ESL) to minimize voltage droop during fast load steps.
- Ultralow equivalent series resistance (ESR) to reduce resistive loss and improve damping of supply rail resonances.
- Wide‑bandwidth ultralow impedance profile to support high di/dt current transients across a broad frequency range.
In practice, low ESL enables the capacitor to remain effective at very high edge rates, where conventional discrete MLCCs on the PCB can be limited by mounting inductance. Low ESR and a flat impedance characteristic help designers maintain tight DC and dynamic voltage regulation at the point of load, even as AI accelerators draw rapidly varying currents.
Each ECAP device is mechanically and dimensionally engineered for substrate embedding rather than simple surface mounting. This includes package thickness, tolerance control and planarity tuned for integration into advanced processor substrates and interposers, which is critical to avoid reliability issues in high‑density chiplet and 2.5D/3D packages.
Typical applications
The EC2005P, EC2025P and EC2006P are intended for use directly under or adjacent to AI‑class processors and high‑end SoCs, where very tight power integrity budgets drive the need for embedded decoupling. Typical use cases include:
- Core and cache rail decoupling for large AI accelerators (GPU, custom AI ASIC, NPU) operating at high current densities.
- High‑speed digital core rails in HPC CPUs and data‑center class SoCs.
- Multi‑rail power delivery in chiplet‑based architectures where vertical power delivery is used to minimize PDN loop inductance.
- Advanced networking and switch ASICs with similar fast transient behavior to AI accelerators.
In these environments, board‑level decoupling alone often cannot provide the required combination of low inductance and high capacitance directly at the die. Embedding ECAPs into the substrate shortens the electrical distance between the silicon and the decoupling network, reducing parasitics and improving the effectiveness of the overall power delivery network.
Technical highlights
The ECAP concept combines silicon‑based capacitor structures with packaging optimized for embedding rather than discrete PCB assembly. For PDN design, the most relevant technical highlights are:
- Capacitance density: tens of microfarads in a few square millimeters, enabling substantial decoupling capacitance very close to the die.
- Embedded form factor: 2 mm × 2 mm up to 4 mm × 4 mm footprints designed to fit within substrate keep‑out and routing constraints.
- Ultralow ESL and ESR: supports wideband decoupling and reduces the need for large “capacitor farms” of discrete MLCCs around the package.
- Power integrity focus: the impedance characteristics are tuned to complement vertical power delivery architectures such as Empower’s Crescendo platform.
For design engineers, this means these capacitors can be treated as part of the on‑package PDN rather than as standard PCB components. They are especially valuable for suppressing mid‑ to high‑frequency impedance peaks that arise from the interaction of on‑die decoupling, package parasitics and PCB‑mounted capacitors.
Where exact electrical limits (voltage rating, detailed frequency response, reliability data) are required for qualification and simulation, these should be taken from the manufacturer datasheet and characterization reports according to the target processor and substrate technology.
Design‑in notes for engineers
When considering ECAPs for a next‑generation AI or HPC design, engineers should focus on how the embedded capacitors fit into the overall PDN strategy rather than treating them as a simple replacement for PCB‑mounted MLCCs:
- Plan for substrate integration early: ECAP footprints and keep‑out areas must be coordinated with substrate layout, via fields and chiplet placement. Late‑stage changes are difficult once the package stack‑up is fixed.
- Co‑simulate the PDN: include ECAP models alongside on‑die capacitance, package parasitics, vertical power delivery elements and board‑level decoupling. This helps determine the optimal mix and placement for meeting impedance targets.
- Match device size to rail requirements: higher‑capacitance EC2006P devices may be allocated to the most demanding core rails, while EC2005P or EC2025P devices can be used on auxiliary or moderately loaded rails where area is constrained.
- Consider thermal and mechanical aspects: embedded components must withstand the same reflow, underfill and thermal cycling environment as the processor package. Use the manufacturer’s guidance on maximum operating conditions and stack‑up compatibility.
- Coordinate with voltage regulator architecture: when using vertical power delivery platforms such as Empower’s Crescendo, the ECAP placement and values can be tuned to minimize PDN loop inductance and optimize transient response from the integrated voltage regulators to the die.
For purchasing and sourcing teams, it is important to recognize that ECAPs are not drop‑in alternatives to standard SMD capacitors. They are typically qualified as part of a specific package design and processor program. Long‑term supply agreements, lifecycle expectations and second‑source strategies should therefore be aligned with the AI/HPC platform roadmap.
Source
This article is based on information provided by Empower Semiconductor in their official press release announcing the EC2005P, EC2025P and EC2006P embedded silicon capacitors for AI and HPC applications, complemented by general power integrity design considerations that apply to on‑package decoupling solutions.
