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    Benefits of Tantalum Powder Stress–Strain Curve Evaluation vs Conventional Wet Test

    Electrolyte Selection and Performance in Supercapacitors

    Connector PCB Design Challenges

    Researchers Demonstrated High Energy Ceramic Capacitors Stable in Wide Temperature Range

    Stackpole Offers High Voltage Plate Resistors up to 40KV

    How to Manage Supercapacitors Leakage Current and Self Discharge 

    Qualification of Commercial Supercapacitors for Space Applications

    Experimental Evaluation of Wear Failures in SMD Inductors

    Resonant Capacitors in High-Power Resonant Circuits

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Optimizing Decoupling Capacitors

19.5.2020
Reading Time: 1 min read
A A

Learn how to optimize decoupling capacitors for the best cost vs. performance using flat target impedance design methods.

Impedance peaks caused by parallel L-C resonances in the power distribution network (PDN) are potential sources of power rail ripple and increased EMI. Bulk capacitors must be selected to insure power supply stability while high frequency decoupling must insure the required bandwidth at the Load.

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Simple SPICE simulations fail to account for PCB parasitics and often result in the wrong selection of decoupling capacitors. Utilizing EM models of the PDN and combining them with power supply state space models and the spectral requirements of the load result in good agreement with measurements.

Optimizing this PDN ecosystem shows that designing for flat impedance is the best way to achieve the lowest noise on the power rail with the minimum number of capacitors.

related video:

Measuring, Modeling, Simulating Capacitors and Inductors

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Source: Picotest

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