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    High Voltage MLCCs Meeting the Growing Demand for Efficiency in Power Conversion

    Bourns Releases High Power High Ripple Chokes

    KYOCERA AVX Releases Hermaphroditic WTW and WTB Connectors

    Radiation Tolerance of Tantalum and Ceramic Capacitors

    TDK Releases Compact Polypropylene Film Capacitors for Resonant Topologies

    Percolation Phenomenon and Reliability of Molded Power Inductors in DC/DC converters

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USB 3.0 Connectors – Architecture, Protocol and Power Management

14.9.2021
Reading Time: 3 mins read
A A

Architecture: from High-Speed to Super-Speed
USB 3.0 consists of a physical super-speed bus in addition to the physical USB 2.0 bus (as illustrated by Figure 2.119). The protocol defines a dual simplex signalling mechanism with a rate of 5 Gbits/s. This enables the simultaneous transfer of data to and from the device, as opposed to the single duplex unidirectional USB 2.0 bus.

Fig. 2.132: USB 3.0 architecture

It is beyond the scope of this article to describe the full USB 3.0 architecture in detail. However, it is important to note that it was inspired by the layered PCIe architecture and the OSI model. Therefore, it includes a physical layer (PHY), a link layer and a protocol layer.

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Separate data lanes used for up and download enable reading and storing files at the same time and therefore offer a much higher data rate, up to 4.8 Gbits/s (versus 480 Mb/s for USB 2.0).

Power Management
USB 3.0 provides enhanced power management capabilities. With up to 150 mA per unit (+50 % compared to USB 2.0) and up to 6 units together, USB 3.0 can carry up to 900 mA, versus 500 mA with USB 2.0. This means a total 80% increase compared to USB 2.0.

There again, this article does not aim to describe how this works in detail, but it is worth noting that while USB 3.0 requires more power when active, it still consumes less power in the end. Indeed, its higher data rate and various power efficiency features let it remain far less active than in the High-Speed Mode. (See Figure 2.133 which compares power consumption during data transfer in High-Speed and Super-Speed Modes).

Fig. 2.133: Power consumption: comparison between High Speed mode & Super Speed mode

Backward Compatibility
As always with USB, the architecture is designed to ensure the electrical and mechanical backward compatibility with former USB versions (1.1 and 2.0). For example, a USB 3.0 compliant host will communicate with a device at the highest rate supported by the said device. Reciprocally: a USB 3.0 compliant device will function at USB 2.0 rate when plugged into a USB 2.0 host.

Tab. 2.10: USB connectors and mating parts – backwards compatibility from USB 3.0 to USB 2.0

This backward compatibility remains a major advantage compared to all other connection protocols available on the market. Indeed, it avoids obsolescence of existing products extending their life in the field. This is especially true for industrial applications where the life cycle has nothing to do with consumer goods.

Fig. 2.134: Backward compatibility

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Source: Wurth elektronik

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