Silicon Capacitors and Integrated Passives Dossier

The next decoupling breakthrough may not be another capacitor on the board. It may be capacitance built into the package.

The Silicon Capacitors and Integrated Passives Technology Dossier 10/26 examines when passive functions should remain discrete—and when they should move into the substrate, interposer or die. It connects silicon capacitor technology, thin-film integrated passive devices, embedded components, precision networks and integrated protection to the architectures that make integration worthwhile.

From high-current AI accelerator power delivery to automotive interfaces, RF modules and implantable medical systems, the question is no longer simply how much capacitance fits into a footprint. It is how much useful electrical performance survives the mounting geometry, operating conditions, assembly process and qualification requirements.

This dossier brings those decisions together with named suppliers, example parts, published specifications, integration economics and a clearly separated view of production technologies and emerging roadmaps.

Why this matters now

Three decisions are converging at the component–package boundary

• AI power delivery is changing where capacitance belongs. As accelerator currents increase, the electrical path between the capacitor and the load becomes a limiting factor. Land-side, die-side, interposer and embedded capacitance are becoming distinct layers of the power delivery network—not interchangeable replacements for the board-level capacitor bank.

• Integration changes the comparison with discrete components. Nominal capacitance and purchase price tell only part of the story. Effective capacitance under operating conditions, loop inductance, board area, placement count, matching and assembly yield can change which solution delivers the better system result.

• Qualification and sourcing must follow the construction. A monolithic silicon capacitor, a ceramic array and an embedded passive network can perform similar functions while requiring different qualification evidence, manufacturing partners and lifecycle planning. Integration can reduce part count while increasing dependence on a specific process or supplier.

Choosing integration late can turn an electrical improvement into a packaging, qualification or supply-chain problem. This dossier puts those trade-offs into the architecture discussion before the design is locked.

What you get

What’s inside

Sixteen chapters connecting integrated-passive technology to practical design, qualification and sourcing decisions.

• Silicon capacitor construction and performance—from planar MIS/MOS and MIM structures to deep-trench and nanostructured approaches, with density, voltage, thickness, ESR, ESL, stability, leakage and lifetime considered together.

• Power delivery architecture mapping—showing the roles of board-level, land-side, die-side, interposer and on-die capacitance, and why placement can matter more than the nominal value.

• Thin-film integrated passive devices—covering silicon and glass platforms, monolithic resistor–inductor–capacitor integration, precision matching and the applications where IPDs offer an advantage over discrete networks.

• Embedded and in-substrate passives—including PCB embedding, package substrates and interposers, with a dedicated silicon-versus-Class II MLCC comparison.

• Integrated networks, arrays and LTCC modules—connecting resistor ratio performance, capacitor arrays, R-C networks and RF integration to selection and sourcing decisions.

• The economics of integration—examining placement cost, bill-of-materials simplification, board area, yield, rework, non-recurring engineering costs, second sourcing and lifecycle exposure.

• Integrated EMI/EMC and circuit protection—covering filter topologies, common-mode filters, ESD arrays and interface-specific selection, with attention to parasitics and signal loading.

• Reliability and qualification clarity—explaining the AEC-Q200, AEC-Q100 and AEC-Q101 distinctions, alongside embedded-component standards, assembly sensitivity and application-specific derating.

• A dedicated AI power-delivery deep dive—exploring silicon capacitors in vertical power delivery for kilowatt-class accelerators and the growing connection between capacitance, regulation and advanced packaging.

• Application examples and technology roadmaps—covering AI accelerator PDNs, automotive zonal interfaces, implantable and RF systems, plus emerging glass substrates, high-density dielectrics and power-delivery integration.

• A segment-specific supplier and supply-chain map—distinguishing silicon capacitor manufacturers, thin-film specialists, substrate makers, foundries and protection-device suppliers, while explicitly identifying gaps and conflicting market estimates.