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    Designing a 2 kW LLC Transformer with Integrated Resonant Inductor

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    Designing a 2 kW LLC Transformer with Integrated Resonant Inductor

    Middle East Conflict: The Potential Impact to Passive Components

    Inductor Technology Dossier

    Coilcraft Releases TLVR Inductors for High Density VRMs and PoL Converters

    Rutheniums Critical Role in Passive Component Supply Chains

    Bourns Expands its Modular Contacts for Power-Dense Systems

    Murata to Decouple China Rare Earth Supply in 3 Years

    Samtec AcceleRate Slim ARC6 Cable Assemblies with New Signaling Options

    Hirose Electric to Establish Automotive Connector Plant in India

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    How Modern Tools Model Magnetic Components for Power Electronics

    Advanced Loss Modeling for Planar Magnetics in the Frenetic Planar Tool

    2026 Power Magnetics Design Trends: Flyback, DAB and Planar

    Enabling Software‑Defined Vehicle Architectures: Automotive Ethernet and Zonal Smart Power

    Calculating Resistance Value of a Flyback RC Snubber 

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IMEC Demonstrated How to Reduce Ruthenium Metal Line Resistance at Tight Metal Pitches

11.7.2022
Reading Time: 2 mins read
A A
Cross-section TEMs of Ru lines with 18nm metal pitch: (left) AR 3, (right) AR 6. The TEMs demonstrate a nearly vertical profile of the Ru lines and scalability of the current scheme towards higher ARs. Source: IMEC

Cross-section TEMs of Ru lines with 18nm metal pitch: (left) AR 3, (right) AR 6. The TEMs demonstrate a nearly vertical profile of the Ru lines and scalability of the current scheme towards higher ARs. Source: IMEC

IMEC, a world-leading research and innovation hub in nanoelectronics and digital technologies, presented at the 2022 IEEE International Interconnect Technology Conference (IITC 2022) options to reduce the metal line resistance at tight metal pitches, mitigating the resistance / capacitance (RC) increase of future interconnects using direct metal patterning.

For the first time, high aspect ratio (AR=6) processing of ruthenium (Ru) in a semi-damascene fashion is experimentally shown to result in about 40% resistance reduction without sacrificing area. Additional simulations confirm the benefits at circuit level in combination with airgaps as dielectrics. A complementary experimental study shows that the reliability of semi-damascene with airgaps is competitive when compared to dual-damascene with low-k dielectrics.

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After providing the first experimental demonstration of a functional two-metal-level semi-damascene module at 18nm metal pitch, AR=3, with fully self-aligned vias at VLSI 2022, imec proposes to extend this integration scheme to further reduce the line resistance of the Ru interconnects, while keeping the same footprint. This can be achieved by high-AR processing of the Ru lines using an advanced subtractive metal etch process.

Zsolt Tokei: “We measured a significant line resistance reduction of about 40% on Ru lines with AR=6 compared to lines with conventional AR=3. In addition, we showed the benefits at circuit level of implementing high-AR semi-damascene lines with airgaps.” In a benchmark study, IMEC also demonstrated that the semi-damascene flow with airgaps is reliable with more than 10 years lifetime.

“With no less than 10 oral presentations at this year’s IITC, addressing the main challenges in interconnect scaling, IMEC has a proven path to push the interconnect roadmap for the coming ten years,” concludes Zsolt Tokei.

“The papers cover advances in semi-damascene integration as a promising interconnect scheme for future logic nodes, memory technologies and highlight progress in middle-of-line (MOL) metallization schemes, dielectrics, alternative metals exploration, and reliability.”

Related

Source: IITC 2022

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