High-Precision Hyperdimensional Computing with Multi-Level Ferroelectric HZO Capacitors

The study by Ella Paasio and co-authors, involving researchers from the University of Helsinki, Technical University of Munich, University of Padua and other collaborating institutions, was published open access in Microsystems & Nanoengineering in September 2026.

It demonstrates how high-polarization hafnium-zirconium oxide ferroelectric capacitors can support dense, low-power capacitive in-memory computing for hyperdimensional computing tasks.

Introduction

Artificial intelligence and edge-computing workloads are increasingly constrained by the energy and latency required to move data between processors and memory. In-memory computing addresses this “memory wall” by storing information and performing selected arithmetic operations directly within memory arrays.

This paper investigates capacitive in-memory computing based on ferroelectric capacitors rather than the more common current-based resistive memory devices. The approach uses the non-volatile polarization of ferroelectric hafnium-zirconium oxide, $\mathrm{Hf}_{0.5}\mathrm{Zr}_{0.5}\mathrm{O}_{2}$, commonly abbreviated as HZO, to program multiple stable capacitance states in a single capacitor.

The central challenge is not merely obtaining many analog states. The states must be sufficiently separated, reproducible and linear to support reliable computation. The authors therefore combine interface-controlled thin-film fabrication, thermal engineering, electrical characterization, structural analysis and hardware-calibrated computing simulations.

Key points

• The researchers fabricated metal-ferroelectric-insulator-metal capacitors using a TiN/HZO/$\mathrm{Al}_{2}\mathrm{O}_{3}/$Ti/Au stack.
• The 10 nm HZO layer and 30 nm TiN bottom electrode were deposited in a cluster atomic-layer-deposition system without a vacuum break, helping to preserve a clean HZO/TiN interface.
• Two rapid-thermal-processing conditions were evaluated: 450 °C for back-end-of-line-compatible processing and 600 °C to explore a higher thermal budget.
• The 600 °C devices reached a remanent polarization of $2P_\mathrm{r}=75\,\mathrm{\mu C/cm^2}$ and sustained operation up to 5.7 V.
• The higher-temperature capacitors provided 32 well-separated programmable polarization states, corresponding to 5-bit storage in one device.
• The 450 °C capacitors supported 16 programmable states, limited mainly by their lower oxide-breakdown voltage.
• Polarization produced a near-linear modulation of capacitance at low read voltage, enabling non-destructive capacitance-based state sensing.
• Simulated capacitive multiply-accumulate operations showed that state linearity and distribution width are as important as nominal bit density.
• Three 5-bit FeCAPs were used to represent one 15-bit value in a hyperdimensional-computing classifier.
• The resulting system achieved 92.3% inference accuracy on the ISOLET spoken-letter dataset and required 2.3 times less area than a binary implementation reaching 84.1% accuracy.

Extended summary

The work focuses on ferroelectric capacitors as analog storage and computing elements. In a conventional von Neumann architecture, data must repeatedly travel between separate memory and processing units. This movement consumes energy, introduces latency and becomes particularly costly for matrix-vector operations used in machine learning. Capacitive in-memory computing seeks to reduce that transfer by encoding a weight in a capacitor and carrying out multiplication through charge-domain operation.

In the proposed concept, the programmed polarization state of a ferroelectric capacitor controls its capacitance. An applied input voltage then creates a charge proportional to the capacitance, allowing the device to perform the fundamental analog relationship

$Q=V \times C$

In an array, charge contributions from several capacitors can be accumulated on a shared line and converted to a digital result by an analog-to-digital converter. Unlike a current-domain crossbar, this method does not require continuous current flow through the memory device during the compute step. The authors identify this as an important route toward lower active power and reduced sensitivity to some current-domain non-idealities.

The device stack was a metal-ferroelectric-insulator-metal structure consisting of TiN/HZO/$\mathrm{Al}_{2}\mathrm{O}_{3}$/Ti/Au. The TiN bottom electrode was 30 nm thick, the HZO ferroelectric layer was 10 nm thick and the alumina layer was 1.2 nm thick. A key process feature was vacuum-integrated deposition of the TiN and HZO layers in an Applied Picosun single-wafer cluster atomic-layer-deposition tool. Avoiding ambient exposure between nitride and oxide deposition was intended to reduce carbon contamination, uncontrolled TiN oxidation and interface-related charge traps.

The authors compared rapid thermal processing at 450 °C and 600 °C for 30 seconds in nitrogen. The 450 °C condition is relevant to complementary metal-oxide-semiconductor back-end-of-line integration, where temperatures below 500 °C are generally required. The 600 °C process offered a larger thermal budget and was used to evaluate the highest obtainable ferroelectric and analog-memory performance.

Electrical measurements were performed using the positive-up negative-down method. This technique separates switching current from non-switching current, enabling the ferroelectric polarization response to be extracted. Both annealing conditions produced robust ferroelectric switching, but the 600 °C sample achieved stronger polarization and a higher breakdown voltage. At a 4 V write voltage, the remanent polarization increased from 22 $\mathrm{\mu C/cm^2}$ for the 450 °C device to 32 $\mathrm{\mu C/cm^2}$for the 600 °C device. At voltages above 5.5 V, the 600 °C sample achieved $2P_\mathrm{r}$ values above 70 $\mathrm{\mu C/cm^2},$ with the paper reporting a maximum value of 75 $\mathrm{\mu C/cm^2}$.

The increased breakdown margin was essential because it widened the usable write-voltage range. The 600 °C capacitor could sustain reliable operation up to 5.7 V, while the 450 °C sample experienced oxide breakdown at 5.2 V. This difference allowed the higher-temperature device to provide 32 stable analog states using programming pulses separated by 0.1 V. The lower-temperature device provided 16 states. In digital terminology, these results correspond to 5-bit and 4-bit storage capability, respectively.

However, the authors show that the number of states alone is not an adequate measure of computational usefulness. The states must have low overlap, predictable spacing and reasonably symmetric potentiation and depression behavior. State distributions tended to cluster at lower programming voltages, whereas stronger linearity and clearer separation emerged at higher voltages. This creates an engineering trade-off: a broad voltage range can provide more stored levels, while a restricted range may deliver more accurate analog multiplication.

Capacitance rather than polarization was selected as the practical computing variable. The capacitance-voltage data exhibited the butterfly-shaped behavior typical of ferroelectric capacitors, and the zero-voltage capacitance showed a highly linear relationship with polarization. The authors fitted the following relationship:

$C(\mathrm{pF})=-0.48\left(\frac{\mathrm{\mu m^2}}{\mathrm{cV}}\right)\cdot P\left(\frac{\mathrm{\mu C}}{\mathrm{cm^2}}\right)+C_0(\mathrm{pF})$

where

$C_0=872\,\mathrm{pF}$

This approximately linear capacitance response is important because it enables programmed polarization states to map to analog weights in a charge-domain computing array. The reported optimum read-voltage region for state linearity was between -0.3 V and 0.5 V. Low-voltage sensing is also favorable because it reduces the risk of disturbing the ferroelectric polarization during readout.

Structural measurements supported the electrical findings. Grazing-incidence X-ray diffraction identified a mixture of monoclinic, tetragonal and orthorhombic HZO phases. The orthorhombic phase is associated with ferroelectricity, and the 600 °C sample showed about 2% more combined ferroelectric tetragonal and orthorhombic phase than the 450 °C sample. Both devices exhibited a relatively high ferroelectric-phase fraction and wake-up-free hysteresis behavior.

Transmission electron microscopy showed sharply defined interfaces and a crystalline HZO layer in the 600 °C sample. X-ray photoelectron spectroscopy depth profiling did not identify a carbon peak at either HZO interface, consistent with the intended benefit of uninterrupted vacuum processing. The measurements also indicated oxygen-vacancy-rich behavior near the alumina/HZO interface and a reduction of hafnium and zirconium oxidation states near the HZO/TiN interface, attributed to oxygen scavenging by TiN during thermal processing.

For computing evaluation, the authors used experimentally derived distributions of the analog polarization states and applied Monte Carlo simulations to assess multiply-accumulate accuracy. The simulated system used analog input voltages for one operand and programmed FeCAP capacitance states for the other. The output charge was digitized using equidistant decision boundaries.

At full 5-bit FeCAP resolution, variations among the 32 states and asymmetric charge behavior caused deviations from ideal multiplication. Reducing the input and memory resolution improved accuracy by increasing the margin between quantization levels. More importantly, the study found that selecting a subset of strongly linear states could yield mathematically correct 2-bit-by-2-bit multiplication without observed deviations. The result underlines that accurate analog computing depends on state linearity and tight state distributions, not simply on the maximum number of programmable levels.

The article then applies the devices to hyperdimensional computing, an error-tolerant computing approach that represents data as high-dimensional vectors called hypervectors. The researchers used random-projection encoding and iterative training on the ISOLET dataset, which contains spoken letters. Three 5-bit ferroelectric capacitors stored a single 15-bit fixed-point number.

With vectors containing 1,000 elements, the FeCAP-based 15-bit implementation achieved 92.3% inference accuracy. A binary encoding system constrained to the same area could use 3,008 vector elements but achieved only 77.4% accuracy. Increasing the binary vector dimension to 7,008 improved accuracy to 84.1%, but required 2.3 times more area than the multi-level FeCAP solution. The study therefore demonstrates that higher bit density per device can reduce the vector dimension and storage area needed for a high-accuracy hyperdimensional-computing task.

The authors also estimate write and read energy. The maximum state-to-state programming transition, from -5.7 V to 5.7 V, was associated with a write energy of approximately 200 nJ for one large experimental capacitor. A binary implementation carrying equivalent information would require five capacitors and was estimated to need 500 nJ in total. The write-energy expression used in the article is

$E_\mathrm{write}=A\cdot\int_{-P}^{P}V(P)\,dP\approx200\,\mathrm{nJ}$

The read energy follows the familiar capacitive relation

$E_\mathrm{read}=\frac{1}{2}CV^2$

At a 0.1 V read voltage, the reported energy was approximately 4.3 pJ for the large experimental device. The authors further estimate that scaling the capacitor from $200\,\mathrm{\mu m}\times200\,\mathrm{\mu m}$ to $2\,\mathrm{\mu m}\times2\,\mathrm{\mu m}$ could reduce read energy to approximately 0.43 fJ and write energy to approximately 20 pJ.

$200\,\mathrm{\mu m}\times200\,\mathrm{\mu m}=40000\,\mathrm{\mu m^2}$

$2\,\mathrm{\mu m}\times2\,\mathrm{\mu m}=4\,\mathrm{\mu m^2}$

$E_{\mathrm{read},2\mathrm{um}}\approx0.43\,\mathrm{fJ}$

$E_{\mathrm{write},2\mathrm{um}}\approx20\,\mathrm{pJ}$

These projections emphasize that device scaling is necessary before the full energy advantages of capacitive in-memory computing can be realized. At smaller dimensions, parasitic capacitances become a more significant system-level challenge and may affect computational accuracy.

The reliability analysis examined fatigue, imprint and defect-related effects under repeated electrical stress. The 600 °C devices endured more than $10^9$ cycles when tested with a 4.5 V dynamic hysteresis measurement condition. The authors observed fatigue, expressed as reduced remanent polarization, as well as changes in coercive behavior consistent with oxygen-vacancy generation or redistribution. The paper notes that lower-voltage stressing produced stronger fatigue while delaying hard breakdown, demonstrating the complex relationship between operating voltage, domain pinning and oxide reliability.

The study also examined how analog-state errors affect hyperdimensional-computing accuracy. For the 5-bit, 32-state FeCAP, the maximum state error probability was 4.2%. When variation was introduced only into test vectors, the inference accuracy remained within ±0.5 percentage points of the ideal 92.3% result. Errors in class vectors, which effectively store the trained model, had a larger impact: mean accuracy fell to about 86%. Errors in both test and class vectors reduced average accuracy to 83.3%.

The authors propose a mixed-precision strategy to manage this sensitivity. More error-sensitive class vectors could be stored using 4-bit FeCAP operation with 16 states, while test vectors could retain the higher density of 5-bit storage. The paper reports a maximum error probability of $3.7\times10^{-4}\%$ for the 4-bit case, indicating that selectively reducing bit density can substantially improve reliability where the stored information is most critical.

Conclusion

This work demonstrates that materials and interface engineering can transform HZO ferroelectric capacitors into multi-level, charge-domain memory elements for in-memory computing. Vacuum-integrated deposition and higher-temperature thermal processing enabled 32 stable states, high remanent polarization and a near-linear polarization-to-capacitance relationship.

The hyperdimensional-computing demonstration shows a practical advantage of multi-bit FeCAP storage: 15-bit values stored across three 5-bit capacitors achieved 92.3% inference accuracy while using substantially less area than the compared binary implementation. The results position ferroelectric capacitors as a potentially dense and energy-efficient alternative for error-tolerant AI workloads.

Important limitations remain. The highest demonstrated performance used a 600 °C anneal, which exceeds the conventional thermal budget for monolithic CMOS back-end-of-line integration. Future work must therefore address lower-temperature processing, scaled capacitor arrays, parasitic capacitance, analog-to-digital conversion overhead, device-to-device variation and long-term retention under application-relevant operating conditions.

Further reading

• What Is a Capacitor?
• Multilayer Ceramic Capacitors MLCC
• MLCC Capacitor Failures, Cracks and Reliability
• AI Data Centers and Passive Components

Source

The information in this article is based on the open-access scientific paper published in Microsystems & Nanoengineering. Engineers should consult the full current paper, supplementary information and applicable device documentation before using the reported values for technology qualification or design release.

References

1. High-precision hyperdimensional computing enabled by in-memory computing using high-polarization ferroelectric Hf0.5Zr0.5O2 capacitors
2. Article PDF