Passive Components Blog has published its Silicon Capacitors and Integrated Passives Technology Dossier 10/26 — an architecture-focused study of when passive functions should remain discrete and when they should move into the substrate, interposer or die.
The next decoupling breakthrough may not be another capacitor on the board. It may be capacitance built into the package. This dossier connects silicon capacitor technology, thin-film integrated passive devices, embedded components, precision networks and integrated protection to the architectures that make integration worthwhile.
For engineering and sourcing teams, the question is not simply how much capacitance fits into a footprint, but how much useful electrical performance survives the mounting geometry, operating conditions, assembly process and qualification requirements. The report brings these considerations together with manufacturing economics, supplier capabilities and application requirements.
From board-level decoupling to land-side, die-side, interposer and on-die capacitance, the dossier maps where integrated passives can improve system performance — and where discrete components remain the better choice.
What the dossier covers
The Silicon Capacitors and Integrated Passives Technology Dossier 10/26 combines architecture mapping, component-technology deep dives, application examples, qualification guidance and market and supply-chain analysis.
Structured into sixteen chapters plus two appendices, the report comprises 79 pages, 33 tables and 12 figures. Named suppliers, example parts and published specifications connect the technology discussion to practical design and sourcing decisions, with production technologies distinguished from emerging roadmaps.
Structural trends and integration architectures
The opening chapters examine the forces moving passive functions closer to the load and deeper into the package. These include AI power-delivery requirements, advanced substrate and interposer integration, thin-film precision networks and the importance of comparing complete system performance rather than nominal component values alone.
An architecture-led view maps the decoupling hierarchy and the roles of board-level, land-side, die-side, interposer and on-die capacitance. It also connects signal-chain and RF integration to system partitioning, explaining why placement, electrical path length and package parasitics can determine whether integration delivers a meaningful advantage.
Silicon capacitors and integrated passive technologies
- Silicon capacitors: planar MIS/MOS and MIM structures, deep-trench technologies and nanostructured approaches, comparing capacitance density, voltage rating, thickness, ESR, ESL, stability, leakage and lifetime alongside assembly and handling constraints.
- Thin-film integrated passive devices: silicon and glass platforms, resistor and dielectric materials, monolithic resistor–inductor–capacitor integration, precision matching and applications where IPDs offer advantages over discrete networks.
- Embedded and in-substrate passives: PCB embedding, package substrates and interposers, including a dedicated comparison of silicon capacitors and Class II MLCCs under relevant electrical and integration constraints.
- Integrated networks, arrays and LTCC modules: resistor ratio tolerance and tracking, capacitor arrays, R-C networks, and low-temperature co-fired ceramic and multilayer organic modules for RF and other integrated functions.
- Integrated EMI/EMC and circuit protection: filter topologies, common-mode filters, ESD arrays and interface-specific selection, with attention to parasitics, insertion loss and signal loading.
Each technology is considered in terms of its electrical role, construction, practical limitations, supplier options and implications for the surrounding system.
The economics of integration: discrete versus integrated
A dedicated chapter moves the comparison beyond component purchase price. It examines placement cost, bill-of-materials simplification, board area, assembly yield, rework, non-recurring engineering costs and total cost of ownership. It also addresses the trade-off between reducing part count and increasing dependence on a particular manufacturing process, supplier or package architecture.
Reliability, qualification and standards
The dossier explains the distinctions between AEC-Q200, AEC-Q100 and AEC-Q101 qualification routes, together with relevant capacitor and embedded-component standards. It connects qualification evidence to component construction, assembly sensitivity, test regimes and application-specific derating rather than treating similarly named integrated products as interchangeable.
Market, suppliers and supply-chain considerations
The supplier landscape is mapped by segment, distinguishing silicon capacitor manufacturers, thin-film specialists, substrate makers, foundries and protection-device suppliers. The report examines market sizing, lead times, pricing, regional manufacturing capacity and published capacity additions, while identifying gaps and conflicting market estimates.
Silicon capacitors in vertical power delivery for AI accelerators
A dedicated deep dive examines silicon capacitors in vertical power delivery for kilowatt-class AI accelerators. It considers where capacitance belongs within the package, how capacitor integration connects with regulation and advanced packaging, and which electrical, manufacturing and sourcing challenges remain open. Board-level and package-level capacitance are treated as different layers of the power-delivery network, not interchangeable replacements.
Application examples and next-generation technologies
Application chapters cover AI accelerator power-delivery networks, automotive zonal gateway interfaces, implantable systems and RF modules, with additional cases tied to named parts and published requirements. The forward-looking chapter examines glass substrates, high-density dielectrics, power-delivery integration and RF packaging roadmaps, before translating these developments into engineering, procurement and strategic implications.
Contents
| Chapter | Title |
|---|---|
| 1 | Structural Trends Shaping Integrated Passives in 2026 |
| 2 | Market and Supply-Chain Environment |
| 3 | Architectures and the Role of Integrated Passives |
| 4 | Silicon Capacitors: Construction, Density and Electrical Behaviour |
| 5 | Thin-Film Integrated Passive Devices on Silicon and Glass |
| 6 | Embedded and In-Substrate Passives |
| 7 | Integrated Passive Networks, Arrays and LTCC Modules |
| 8 | The Economics of Integration: Discrete versus Integrated |
| 9 | Integrated EMI/EMC and Circuit Protection |
| 10 | Reliability, Qualification and Standards |
| 11 | Deep Dive: Silicon Capacitors in VPD for kW AI Accelerators |
| 12 | Application Examples |
| 13 | Next-Generation Technologies |
| 14 | Design and Business Implications |
| 15 | Key Takeaways |
| 16 | About the Dossier |
| Appendix A | Abbreviations and Acronyms |
| Appendix B | Companies and Organisations Cited |
| References | Source references |
Key questions the dossier answers
- When should passive functions remain discrete, and when does integration into a substrate, interposer or die deliver enough electrical, space or manufacturing value to justify the additional complexity?
- How do planar, deep-trench and nanostructured silicon capacitors compare in density, voltage capability, parasitics, stability and assembly requirements?
- Where do board-level, land-side, die-side, interposer and on-die capacitors belong in the power-delivery hierarchy — and why can placement matter more than nominal capacitance?
- How should silicon capacitors be compared with Class II MLCCs when effective capacitance, mounting geometry and embedding constraints are included?
- When do thin-film IPDs, matched resistor networks, capacitor arrays and LTCC modules offer a stronger solution than discrete components?
- How do placement savings, board area, yield, rework and development costs change the economics of integration?
- Which qualification route applies to a particular construction, and what additional evidence is needed for automotive, medical or embedded applications?
- How does vertical power delivery for AI accelerators change the relationship between capacitance, regulation and advanced packaging?
- Which suppliers and manufacturing partners serve each segment, and where do custom-process dependence, second sourcing and lifecycle risk become architecture-level decisions?
Who needs this on their desk
- Hardware and power-integrity engineers designing accelerator, processor and FPGA power-delivery networks who need to evaluate capacitance, placement and package parasitics together.
- Advanced-packaging and substrate engineers assessing embedded components, interposer capacitance and land-side or die-side integration.
- RF and precision-analog designers comparing discrete networks with thin-film IPDs, matched arrays and LTCC modules.
- Automotive and medical component engineers connecting electrical performance with qualification evidence, assembly constraints and long-life reliability.
- Procurement and supply-chain teams evaluating supplier capabilities, custom-process dependence, second-source options and lifecycle exposure.
- Product and technology leaders deciding whether integration delivers enough performance, space or manufacturing value to justify its development cost and sourcing commitments.
Availability
The Silicon Capacitors and Integrated Passives Technology Dossier 10/26 is available now from passive-components.eu at 699 EUR as a paid PDF download. Delivery is instant after payment, with an invoice supplied by email.
Learn more and purchase the report:
For other available reports, visit the Technology Dossiers page on the Passive Components Blog.
