Zowie Technology, Taiwan has outlined an ultra-thin multilayer polymer aluminum electrolytic capacitor (MLPC) platform intended for embedded power-delivery-network applications in AI accelerators, GPUs, high-performance ASICs and related HPC hardware.
The development is notable not simply for low-ESR polymer capacitance, but for a double-sided electrode concept intended to shorten the power-and-ground current path when the component is embedded within a PCB or substrate.
The announcement reflects a broader shift in high-current processor PDNs: available board area and component height are increasingly constrained, while faster load steps require effective capacitance at low impedance close to the load. In this environment, an embedded aluminum polymer capacitor must be evaluated as part of the complete interconnect structure, including microvias, planes, package interfaces and the substrate manufacturing process.
Key features and benefits
- Ultra-thin MLPC platform: Zowie is targeting 0.6 mm and 0.8 mm thickness options for embedded-capacitor applications where Z-height is limited.
- Double-sided terminal electrodes: Electrical contacts on both capacitor surfaces are intended to support short vertical connections between power and ground layers through microvias.
- Low-ESR development target: The larger 7343 platform has a stated target ESR of approximately 4.5 to 6 mΩ, subject to the final capacitor construction, voltage rating and measurement conditions.
- High local capacitance in a compact footprint: The 7343 format targets approximately 140 to 220 µF, enabling local energy storage and mid-to-low-frequency transient support near high-current loads.
- Distributed decoupling option: The smaller 3528 platform targets approximately 50 µF and is positioned for distributed placement across several power rails or local load hot spots.
- Embedded-system focus: The concept addresses not only capacitance density, but also loop inductance, placement distance, available board surface and power-delivery density.
- Low-stress package direction: Zowie identifies CTE matching and lower mechanical stress after lamination as key requirements for reliable PCB or substrate embedding.
MLPC platform overview
| Parameter | 7343 ultra-thin MLPC | 3528 compact MLPC |
|---|---|---|
| Nominal footprint | Approximately 7.3 × 4.3 mm | Approximately 3.5 × 2.8 mm |
| Target thickness | 0.6 to 0.8 mm | 0.6 to 0.8 mm |
| Target capacitance | Approximately 140 to 220 µF | Approximately 50 µF |
| Target ESR | Approximately 4.5 to 6 mΩ | To be confirmed with final structure |
| Intended PDN role | Local high-capacitance decoupling | Distributed embedded decoupling |
The published values are development targets rather than released production ratings. Final electrical specifications, including rated voltage, capacitance tolerance, impedance-versus-frequency behaviour, leakage current and temperature characteristics, should therefore be verified in the applicable manufacturer datasheet and qualification documentation.
Why double-sided electrodes matter
Conventional surface-mount polymer capacitors normally connect through terminals on one side of the package. This works well for board-level assembly, but it can limit the electrical benefit of embedding if the current still has to travel laterally from a component edge through copper routing and vias before reaching the power and ground planes.
Zowie’s proposed MLPC structure places electrodes on both the top and bottom faces. In an embedded structure, this could allow one side to connect toward a power layer and the opposite side toward a ground layer through short microvias. The intended advantage is a more direct vertical current loop, potentially reducing the total parasitic inductance contributed by pads, traces, vias, planes and package interconnections.
The expected system benefit is therefore not defined by capacitance alone. A lower-inductance connection can improve how much of the nominal capacitance remains effective during a fast load transient, particularly in the frequency region between bulk energy storage and the highest-frequency decoupling handled by MLCCs closest to the processor package.
MLPCs in a hybrid decoupling network
Zowie does not position the MLPC as a direct replacement for all MLCCs. Instead, the intended architecture combines multiple capacitor technologies according to their effective frequency range and physical location.
| PDN function | Likely capacitor approach | Design objective |
|---|---|---|
| Bulk energy storage | Larger polymer or other bulk capacitors, located further from the processor | Support lower-frequency load changes and regulator stability |
| Local mid-to-low-frequency decoupling | Embedded ultra-thin MLPCs | Provide substantial local capacitance with low ESR and shorter connections |
| High-frequency decoupling | Low-ESL MLCCs close to package power terminals | Control high-frequency and ultra-high-frequency impedance |
| Package-level decoupling | Package-integrated or substrate-integrated capacitors where available | Minimise the critical current-loop inductance |
For a GPU or AI ASIC, several smaller embedded MLPCs may be more useful than one larger component with the same nominal aggregate capacitance. Distributed placement can place capacitance closer to separate load regions and power rails, reducing the electrical distance to each local transient source.
This is also why a simple “one MLPC replaces a certain number of MLCCs” rule should be avoided. The result depends on the MLCC capacitance under DC bias, individual ESR and ESL, placement, plane geometry, target impedance, VRM control response and the load-transient spectrum.
Relation to established polymer capacitors
The MLPC terminology used in the Zowie announcement describes a multilayer polymer aluminum electrolytic construction intended for embedded integration. It belongs to the wider category of conductive-polymer capacitors, in which the polymer electrolyte helps achieve low ESR compared with conventional wet aluminum electrolytic capacitors.
Established vendors already offer low-profile conductive-polymer capacitor families for demanding board-level power applications. Zowie’s potentially differentiating element is not merely polymer-capacitor performance. It is the stated effort to combine thin package geometry, two-sided terminations, material compatibility and embedded-process validation into an integration route for PCB and substrate-level PDN design.
Typical applications
Potential application areas include:
- AI accelerators and GPU power rails with high transient-current demand
- AI ASICs and custom compute modules
- High-performance server motherboards and accelerator cards
- Networking switches and routers with high-current digital core rails
- FPGA, ASIC and processor modules with severe board-area constraints
- Advanced packaging substrates and embedded-component PCB architectures
- Systems where reducing surface-mounted capacitor count can improve routing access, thermal design or package escape routing
The most credible initial applications are likely to be designs already capable of supporting embedded passive components and fine-pitch microvia processing. The component itself is only one part of the solution; stack-up design, resin flow, cavity formation, laser drilling, via alignment and copper-plating quality will all influence electrical and reliability outcomes.
Reliability and process validation
For embedded capacitors, component qualification must extend beyond conventional surface-mount endurance testing. Zowie identifies several areas requiring validation, including thermal-mechanical analysis, CTE measurement, temperature cycling, high-temperature storage, moisture absorption, reflow performance, lamination tolerance, microvia reliability and cross-sectional failure analysis.
This focus is important because an embedded capacitor becomes part of a composite substrate structure. Differential expansion between the capacitor package, resin system, copper and dielectric layers can concentrate stress at terminals, package edges, resin interfaces and microvia connections. Electrical targets such as capacitance and ESR are necessary, but they are not sufficient evidence of suitability for volume embedded-component manufacturing.
Source
This article is based on Zowie Technology’s August 2026 announcement describing its ultra-thin, double-sided electrode MLPC development platform for embedded AI/HPC power-integrity applications. The reported dimensions, capacitance values and ESR figures are stated development targets and remain subject to final product structure and manufacturer verification.
